This invention relates generally to semiconductor memory devices, and more specifically, to non-volatile memories and memory programming.
Conventional memory arrays, such as an electrically erasable programmable read only memory (EEPROM) array, comprise pluralities of individual memory cells. The memory cells can be programmed for desired logic or memory states. In programming the array, each cell must have either a high or low voltage (i.e., on or off) state. The high voltage state that is desirable is limited by power consumption considerations and physical and materials constraints. The low voltage state that is desirable is likewise limited because it must be differentiated from the high voltage state and, yet, it must not result in cross leakage among neighboring cells in tight memory array cell distributions. The higher the voltage required for programming the high states, the greater the power consumed by the memory cells. Typical programming voltages for non-volatile NAND memory arrays are in the range of 18-20 volts. NAND memory arrays are characterized by having a plurality of series-connected transistors in the bit lines. Additional issues which are created with the use of high programming voltages such as 18-20 volts include the requirement of costly and sometimes elaborate charge pumps. As supply voltages associated with semiconductors continue to decrease below the five-volt supply value, the requirements demanded of charge pumps may not be met. Also, to eliminate a disturbance problem with unselected cells when using a high word line voltage during programming operation, the unselected word line voltage is in the range of 9 to 11 volts. Additionally, a voltage in the range of 3 to 5 volts is applied to the drain of a drain select transistor of the unselected bit lines. These voltages are required to create a self-boosting mechanism in the channels of each of the transistors in the unselected bit lines.
Another form of non-volatile memory array is known as a NOR memory array. NOR memory arrays are characterized by the use of parallel-connected transistors in the bit lines. NOR memory arrays are typically much faster than NAND memory arrays, but NAND memory arrays are typically much more compact and dense. As a result, it is sometimes desired to use both a NOR memory array and a NAND memory array in the same integrated circuit. For example, certain embedded memory applications may be more size critical in a particular application, whereas other applications may be more speed critical. However, a problem exists when trying to utilize both a NAND memory array and a NOR memory on the same integrated circuit. Each type of memory array typically requires a significantly different process to manufacture. For example, NAND memory cells sometime require a self-aligned trench structure in a triple polysilicon process. On the other hand, NOR memory cells typically use a non-self-aligned trench with a double polysilicon process. As a result, many commercial manufacturing processes do not permit a designer to implement both types of memory arrays in a single integrated circuit.